Memory cells as bits are frequently used in integrated circuits and, they often require a major portion of an integrated circuit. Consequently, memory cells are usually designed with minimum area while meeting the required performance and yield targets for the memory. To achieve minimum area, near-minimum device sizes and smaller-than-logic design rules are usually used in memory cells. As a result, memory bit failures due to transistor variation and subtle process defects often determine the yield of the memory and therefore, the yield of the integrated circuit. To better understand the root cause of memory bit fail for memory cell design and allow further process improvement, expensive and often time-consuming and destructive physical failure analysis (PFA) is used after a functional bit failure signature occurs. With continued technology scaling, PFA has become more difficult and improvements in testing capabilities would prove beneficial in the art.